The present invention relates to a cache-coherent non-uniform memory access (CC-NUMA) parallel computer system including a plurality of computing nodes coupled to an interconnection network; and, more particularly, to an apparatus for controlling a cache by using dual-port transaction buffers in the CC-NUMA parallel computer system.
Generally, a cache-coherent non-uniform memory access (CC-NUMA) parallel computer system conforms to a known cache coherence protocol. The CC-NUMA parallel computer system includes a plurality of computing nodes. In the CC-NUMA parallel computer system called a distributed shared memory system, the plurality of computing nodes include physically distributed memory modules corresponding to a logically shared memory, wherein each computing node is a symmetric multiprocessor having at most four processors, a memory and an input/output device.
In the publication of U.S. Pat. No. 5,721,839 entitled xe2x80x9cApparatus and Method for Synchronously Providing a Fullness Indication of a Dual Ported Buffer Situated between Two Asynchronous Busesxe2x80x9d issued on Feb. 24, 1998 to Callison et al., a computer system includes a bridge between a peripheral component interconnect (PCI) bus and an extended industry standard architecture (EISA) bus; and a bridge between the PCI bus and another PCI bus, which have a data buffer to store write and read data. The data buffer is a dual-port buffer consisting of a first-in-first-out (FIFO) memory. The computer system allows two busses coupled to the bridge to independently operate with different clocks.
Further, in the publication of U.S. Pat. No. 5,636,358 entitled xe2x80x9cApparatus and Method for Transferring Data in a Storage Device Including a Dual-Port Bufferxe2x80x9d issued on Jun. 3, 1997 to Brant et al., a computer storage subsystem includes a dual-port buffer memory. The dual-port buffer memory provides two internal data busses: one bus for transferring data between the dual-port buffer memory and the storage units, and the other bus for transferring data between the dual-port buffer memory and a CPU. The throughput of the storage subsystem is roughly equivalent to the bandwidth of the slower of the two busses. The storage subsystem employs a plurality of dual-port buffer memories in parallel to increase the throughput of the storage subsystem and match the bandwidth of the two busses.
Furthermore, in the publication of U.S. Pat. No. 5,860,120 entitled xe2x80x9cDirectory-Based Coherency System Using Two Bits to Maintain Coherence on a Dual Ported Memory Systemxe2x80x9d issued on Jan. 12, 1999 to Young et al., a directory-based cache coherence memory system includes a dual ported system memory shared by multiple processors within the computer system; a plurality of data cache memories, at least one data cache associated with each processor; and first and second memory busses, the first memory bus connecting a first subset of processors and associated data cache memories to a first port of the system memory, and the second memory bus connecting a second subset of processors and associated data cache memories to a second port of the system memory.
There is a problem that a system and apparatus disclosed in the prior art U.S. patents can not effectively perform the cache coherence protocol. Accordingly, it is strongly needed that an apparatus for controlling a cache by using dual-port transaction buffers to effectively perform the cache coherence protocol.
It is, therefore, an object of the present invention to provide an apparatus for controlling a cache by using dual-port transaction buffers that is capable of effectively performing a cache coherence protocol.
In accordance with an aspect of the present invention, there is provided an apparatus for controlling a cache in a computing node, which is located between a node bus and an interconnection network to perform a cache coherence protocol, comprising: a node bus interface means for interfacing with the node bus; an interconnection network interface means for interfacing with the interconnection network; a cache control logic means for controlling the cache to perform the cache coherence protocol; a plurality of first dual-port transaction buffering means coupled between said node bus interface means and said cache control logic means for buffering transaction requested and replied from or to local processors contained in the computing node; and a plurality of second dual-port transaction buffering means coupled between said interconnection network interface means and said cache control logic means for buffering transaction requested and replied from or to remote processors contained in another computing node coupled to the interconnection network.